How To Make A Register That Can Shift Both Ways

Shift Register

A group of flip flops which is used to shop multiple $.25 of data and the information is moved from 1 flip flop to some other is known equally Shift Register. The bits stored in registers shifted when the clock pulse is applied inside and within or outside the registers. To form an n-chip shift register, we have to connect northward number of flip flops. So, the number of $.25 of the binary number is straight proportional to the number of flip flops. The flip flops are connected in such a fashion that the offset flip bomb's output becomes the input of the other flip flop.

A Shift Register can shift the bits either to the left or to the right. A Shift Register, which shifts the bit to the left, is known as "Shift left annals", and information technology shifts the flake to the right, known as "Right left register".

The shift annals is classified into the following types:

Series In Serial Out
Serial In Parallel Out
Parallel In Series Out
Parallel In Parallel Out
Bi-directional Shift Register
Universal Shift Register

Serial IN Serial OUT

In "Serial Input Series Output", the data is shifted "IN" or "OUT" serially. In SISO, a single bit is shifted at a time in either right or left direction under clock control.

Initially, all the flip-flops are set in "reset" condition i.e. Y₃ = Y₂ = Y₁ = Y₀ = 0. If we laissez passer the binary number 1111, the LSB chip of the number is practical offset to the Din scrap. The D3 input of the third flip flop, i.e., FF-3, is directly connected to the serial information input D3. The output Y_iii is passed to the data input d₂ of the side by side flip flop. This process remains the same for the remaining flip flops. The block diagram of the "Serial IN Series OUT" is given below.

Cake Diagram:

Operation

When the clock signal application is disabled, the outputs Y₃ Y₂ Y₁ Y₀ = 0000. The LSB scrap of the number is passed to the data input D_in, i.e., D_iii. We will employ the clock, and this time the value of D₃ is 1. The offset flip flop, i.eastward., FF-3, is gear up, and the give-and-take is stored in the register at the first falling edge of the clock. Now, the stored word is g.

The next bit of the binary number, i.e., one, is passed to the information input D₂. The second flip flop, i.e., FF-2, is gear up, and the word is stored when the next negative border of the clock hits. The stored word is inverse to 1100.

The next bit of the binary number, i.e., i, is passed to the data input D_one, and the clock is applied. The third flip flop, i.due east., FF-ane, is prepare, and the give-and-take is stored when the negative edge of the clock hits once again. The stored give-and-take is inverse to 1110.

Similarly, the last bit of the binary number, i.e., i, is passed to the data input D₀, and the clock is applied. The last flip flop, i.east., FF-0, is set, and the word is stored when the clock's negative edge arrives. The stored word is changed to 1111.

Truth Table

Waveforms

Serial IN Parallel OUT

In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop, and outputs are fetched in a parallel way. The data is passed flake past fleck in the register, and the output remains disabled until the data is non passed to the data input. When the data is passed to the annals, the outputs are enabled, and the flip flops comprise their return value

Below is the block diagram of the 4-chip serial in the parallel-out shift register. The excursion having four D flip-flops contains a articulate and clock signal to reset these iv flip flops. In SIPO, the input of the second flip flop is the output of the first flip flop, and so on. The same clock betoken is applied to each flip bomb since the flip flops synchronize each other. The parallel outputs are used for advice.

Block Diagram

Parallel IN Serial OUT

In the "Parallel IN Series OUT" register, the data is entered in a parallel way, and the outcome comes serially. A four-bit "Parallel IN Series OUT" register is designed below. The input of the flip flop is the output of the previous Flip Flop. The input and outputs are connected through the combinational circuit. Through this combinational circuit, the binary input B₀, B_one, B_ii, B₃ are passed. The shift style and the load mode are the two modes in which the "PISO" circuit works.

Load mode

The bits B₀, B₁, B₂, and B₃ are passed to the respective flip flops when the second, 4th, and 6th "AND" gates are agile. These gates are agile when the shift or load bar line fix to 0. The binary inputs B0, B1, B2, and B3 will exist loaded into the respective flip-flops when the edge of the clock is depression. Thus, parallel loading occurs.

Shift mode

The 2d, 4th, and sixth gates are inactive when the load and shift line set to 0. So, we are non able to load data in a parallel way. At this time, the first, third, and fifth gates will be activated, and the shifting of the data will be left to the right bit. In this way, the "Parallel IN Serial OUT" performance occurs.

Block Diagram

Parallel IN Parallel OUT

In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel manner in the register. The inputs A₀, A₁, A₂, and A_three, are directly passed to the data inputs D₀, D₁, D₂, and D_three of the respective flip flop. The bits of the binary input is loaded to the flip flops when the negative clock edge is practical. The clock pulse is required for loading all the $.25. At the output side, the loaded bits announced.

Cake Diagram

Bidirectional Shift Register

The binary number after shifting each bit of the number to the left by one position will be equivalent to the number produced by multiplying the original number by 2. In the aforementioned way, the binary number after shifting each bit of the number to the right by one position will exist equivalent to the number produced by dividing the original number by 2.

For performing the multiplication and partitioning operation using the shift annals, it is required that the data should be moved in both the direction, i.e., left or right in the register. Such registers are called the "Bidirectional" shift register.

Beneath is the diagram of 4-bit "bidirectional" shift annals where D_R is the "serial correct shift information input", D_L is the "left shift data input", and M is the "manner select input".

Cake Diagram

Operations

1) Shift right operation(M=1)

The outset, third, fifth, and 7th AND gates will exist enabled, but the second, 4th, sixth, and eighth AND gates will be disabled.
The data present on the information input DR is shifted bit by bit from the fourth flip bomb to the get-go flip flop when the clock pulse is applied. In this way, the shift right performance occurs.

2) Shift left operation(M=0)

The 2nd, fourth, sixth and 8th AND gates volition be enabled, only the AND gates first, third, fifth, and seventh volition be disabled.
The data present on the data input DR is shifted bit by bit from the first flip flop to the quaternary flip flop when the clock pulse is applied. In this manner, the shift right operation occurs.

Universal Shift Register

A register where the data is shifted in ane direction is known equally the "uni-directional" shift register. A register in which the data is shifted in both the direction is known as "bi-directional" shift register. A "Universal" shift register is a special type of register that can load the information in a parallel manner and shift that data in both directions, i.east., right and left.

The input One thousand, i.e., the mode command input, is set to 1 to perform the parallel loading performance. If this input gear up to 0, then the serial shifting performance is performed. If we connect the way control input with the ground, then the circuit will work as a "bi-directional" register. The diagram of the universal shift register is given below. When the input is passed to the series input, the register performs the "series left" performance. When the input is passed to the input D, the register performs the series right operation.